Aashish R. Karkhanis



Aashish Karkhanis is an associate with Foley & Lardner LLP. He is a member of the firm’s Electronics Practice. Aashish has over a dozen years of experience across the patent industry, covering patent drafting, prosecution, diligence, and transactions on behalf of leading U.S. and international technology companies.

Aashish specializes in preparing and prosecuting patent applications in the United States and conducting IP due diligence, counseling, and negotiation for patent assets in M&A, IP asset purchases and litigation. His practice also includes legal research informing patent policy of the United States through publications and presentations with Stanford Law School, U.C. Berkeley Engineering and others.

Aashish has prosecuted and transacted patents in a wide range of electrical engineering and computer science fields including artificial intelligence, computer architecture, cryptography, distributed computing, network architecture, semiconductor fabrication and logic, video compression and web technologies.

Prior to joining Foley, Aashish began his career in intellectual property as a patent examiner at the United States Patent and Trademark Office.

Publications and Presentations

  • 19 Stanford Technology Law Review 196 (2016)
  • 15 Wake Forest Journal of Business & Intellectual Property Law 203 (2015)
  • Berkeley Engineering (2015), Stanford Law School (2015), Berkeley Law (2014)
  • Executive Office of the President, “Patent Assertion and U.S. Innovation” (citation, 2013)
  • USPTO Software Partnership Roundtable (Stanford, CA, 2013)


  • Santa Clara University School of Law (J.D., 2013)
    • Intellectual Property Certificate
    • Emery Merit Scholarship; Co-Researcher to Colleen V. Chien
  • Virginia Tech, Computer Engineering (B.S., 2005)
    • Dean’s List
    • Bernard Silverman Scholarship
    • Northrop Grumman Engineering Corporate Scholarship
    • Marshall Hahn Engineering Scholarship


  • California
  • United States Patent and Trademark Office