Girish B. Ratanpal

Technical Specialist, Sr.


Dr. Girish Ratanpal is a technical specialist with Foley & Lardner LLP. He assists attorneys in preparing and prosecuting patent applications, and litigation teams in patent infringement and invalidity analysis related to complex technologies.

He has prepared and prosecuted patent applications in the fields of computer networking, communication, signal processing, medical devices, and consumer electronics, including storage area networks, Fibre Channel networks and switches, audio and video conferencing systems, and implantable cochlear and spinal stimulators. In the fields of electrical engineering, computer engineering, physics, and optics, his patent prosecution application experience includes analog and digital circuits, inter-chip communication circuits, measuring circuits, magneto-hydro-dynamic heat sinks, power conversion circuits, smart cards, secure mobile communications, nuclear magnetic resonance, and stereoscopic displays, microelectromechanical systems (MEMS) displays, and MEMS audio sensors.

He is a member of the Automotive Industry Team at Foley, and has prepared and prosecuted patent applications and managed patent portfolios in automotive technologies such as integrated battery modules, battery power control systems, fuel cells, hybrid power drive systems, exhaust after-treatment systems, and advanced internal combustion engines.


Girish earned his doctorate in electrical engineering from the University of Virginia (Ph.D., 2006). He earned his master’s degree in electrical engineering from State University of New York at Binghamton (M.S., 2000) and his bachelor’s in engineering in industrial electronics from Pune University (B.S., 1997).

Community Engagement

Outside his legal work, Girish had volunteered his time with Project GRAD, a program to introduce computers to students at a low-income middle school; the UVA chapter of Engineering Students Without Borders, where he served as secretary and director and regional coordinator for the South African region; and Computers for Kids. He also served as a reviewer for IEEE Transactions on Dependable and Secure Computing.


  • G. B. Ratanpal, R. D. Williams and T. N. Blalock, “An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks,” IEEE Transactions on Secure and Dependable Computing, vol. 1, issue 3, Jul-Sept. 2004, pp. 179-189.
  • J. G. Delgado-Frias and G. B. Ratanpal, “A VLSI Crossbar Switch with Wrapped Wave Front Arbitration,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Jan 2003, vol. 50, no. 1, pp. 135-41.
  • “A VLSI Wrapped Wave Front Arbiter for Crossbar Switches,” J. G. Delgado-Frias and G. B. Ratanpal, Proceedings of the 11th Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp. 85-88, 2001.